- Exercise 1 . (Flip Flop)
- A flip-flop D samples its input at each rising edge of the clock signal. Suppose we want to
- replace such systematic sampling by a controlled sampling so that new input data is sampled
- only when a control signal CMD is 010. Derivate a structure allowing this controlled sampling.
- Figure 1 – Timing diagram of a flip-flop D with controlled sampling.
- Exercise 2 . (Basics on Architecture)
- We are interested in defining the architecture of a processor PROC. The input signal of PROC,
- x, is sampled at the clock frequency fs. The output signals of PROC are given by the equations
- (1), (2), and (3). Notice that n denotes the signal’s age. For example, xn denotes the n-th sample
- of x. The processor PROC is supposed to be implemented using registers R in addition to
- combinational operators OP1 and OP2 (that perform operations OP1 and OP2, respectively).
- The operator OP2 is commutative.
- yn = OP2(xn;wn2) (1)
- wn = OP2[OP1(wn2);OP1(zn2)] (2)
- zn = OP2[(OP1(yn);OP1(wn)] (3)
- (1) Derivate a parallel architecture for the processor PROC. Notice that ”parallel” architecture
- means that at each graph’s node corresponds a separate operator.
- (2) Suppose propagation delays tOP1 = tOP2 = 25ns. Suppose ideal register delay (tR = 0).
- Derivate the maximal frequency (fmax1) of the proposed PROC.
- (3) If fmax1 < 20 MHz, make changes in your architecture in order to obtain fmax2 20 MHz.
- (4) Try to make changes in order to obtain fmax3 40 MHz. What are your conclusions ?
- (5) Derivate a sequential architecture for the processor PROC. Notice that ”sequential” architecture
- means that it’s based on only one OP1 and only one OP2. Let 1n
- and 2n
- be the
- outputs of OP1 and OP2, respectively. All registers R are supposed to be ideal (tR = 0).
- The proposed architecture should allow processing of input samples x at a rate 10MHz.
- What is the minimal clock frequency ? Sketch a timing diagram showing y, w, z, 1 and
- 2 evolution for two consecutive calculations, i.e. n and n + 1.
- Page 1
- Telecom ParisTech Synchronous Logic Prof. Lirida Naviner
- Exercise 3 . (Basics on Architecture)
- Let be the iterative algorithm presented in the graph of the figure bellow. An iteration consists
- on one step of calculation (represented by cercles) followed by one step of wire multiplexing.
- The calculation step needs 8 operations OP on a set of 16 operands (D0 to D15). Consider
- the sampling period of operands (D0 to D15) is 51:2s. Consider an application requiring 256
- iterations of a such algorithm. Also consider you dispose of registers and fully combinational
- operators OP that perform the operation OP shown in the nodes of the given graph. The
- operators have propagation delay tOP = 250ns. The registers have total delay tR = 2:5ns.
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- OP
- D01
- D03
- D04
- D06
- D09
- D011
- D012
- D014
- D00
- D02
- D05
- D07
- D08
- D010
- D013
- D015
- D0
- D1
- D2
- D3
- D4
- D5
- D6
- D7
- D8
- D9
- D10
- D11
- D12
- D13
- D14
- D15
- Figure 2 – Calculation graph.
- (1) Give the maximal operation frequency fmax accepted by operator OP.
- (2) Give the computation power required by the application (in OP/s).
- (3) Let be the implementation of the algorithm based on only one pipelined operator OP. How
- many pipeline barriers are required ?
- (4) Consider the pipelined operator OP of previous item. Give the sequence of operations for
- two consecutive iterations. What are your conclusions ?

# Synchronous Logic

6/12/2017