Lirida Naviner

Personal webpage

Scientific Production

  • 2018

    N. Maciel, E. Crespo Marques, L. Alves de Barros Naviner and H. Cai, Single-event transient effects on dynamic comparator in 28nm FDSOI CMOS technology, Microelectronics Reliability, October 2018, vol. 88-90, pp. 965-968.

    E. Crespo Marques, N. Maciel, L. Alves de Barros Naviner, H. Cai and J. Yang, Compressed Sensing for Wideband HF Channel Estimation, 4th International Conference on Frontiers of Signal Processing, Poitiers, France, September 2018, pp. 1-5.

    F. Veirano, F. Silveira and L. A. B. Naviner, Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits, IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.

    H. Cai, Y. Wang, L. Alves de Barros Naviner, J. Yang, W. Kang and W. Zhao, Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques, IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.

    Y. Wang, Y. Zhang, Z. Youguang, W. Zhao, H. Cai and L. A. B. Naviner, Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning, To appear in Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, Illinois, USA, May 2018, pp. 23-25.

    F. B. Armelin, L. Alves de Barros Naviner and R. d'Amore, Probability Aware Fault-Injection Approach for SER Estimation, Proceedings of IEEE Latin American Test Symposium (LATS), São Paulo, SP, Brazil, March 2018.

    F. B. Armelin, L. Alves de Barros Naviner and R. d'Amore, Using FPGA self-produced transients to emulate SETs for SER estimation, Proceedings of IEEE Latin American Test Symposium (LATS), São Paulo, SP, Brazil, March 2018.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Exploring Hybrid STT-MTJ/CMOS Energy Solution in Near/Sub-Threshold Regime, IEEE Transactions on Magnetics, February 2018, vol. 54, n° 2, pp. 1-9.

    Y. Wang, Y. Zhang, W. Zhao, Y. Lakys, D. Ravelosona, J.-O. Klein, L. Alves de Barros Naviner and H. Cai, Compact Model of Dielectric Breakdown in Spin Transfer Torque Magnetic Tunnel Junction 6.0, NanoHub, 2018 [PDF].

  • 2017
  • F. Veirano, L. Alves de Barros Naviner and F. Silveira, Optimal Asymmetrical Back Plane Biasing for Energy Efficient Digital Circuits in 28 nm UTBB FD-SOI , Integration, the VLSI Journal, December 2017.

    F. Veirano, L. Alves de Barros Naviner and F. Silveira, Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, December 2017.

    M. Slimani, K. Benkalaia and L. Alves de Barros Naviner, Analysis of Ageing effects on ARTIX7 XILINX FPGA (article) Author, Microelectronics Reliabilit Journal, October 2017.

    M. Slimani, K. Benkalaia and L. Alves de Barros Naviner, Analysis of Ageing effects on ARTIX7 XILINX FPGA, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, September 2017.

    N. Maciel, E. Crespo Marques and L. Alves de Barros Naviner, Sparsity Analysis using a Mixed Approach with Greedy and LS Algorithms on Channel Estimation, International Conference on Frontiers of Signal Processing (ICFSP), Paris, France, September 2017, pp. 91-95.

    H. Cai, W. Kang, Y. Wang, L. Alves de Barros Naviner, J. Yang and W. Zhao, High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects, Applied Science, September 2017, vol. 7, n° 9, pp. 929 (13 pages) [DOI 10.3390/app7090929].

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core, VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on, Bochum, Germany, June 2017.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device, Great Lakes Symposium on VLSI 2017 (GLSVLSI 17), Banff, Canada, May 2017.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology , IEEE Transactions on Circuits and Systems I: Regular Papers, April 2017, vol. 64, n° 4, pp. 847-857.

    Y. Wang, H. Cai, L. Alves de Barros Naviner and W. Zhao, A Non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction-Based Circuits, IEEE Transactions on Magnetics, March 2017, vol. 53, n° 3, pp. 1-6 [DOI 10.1109/TMAG.2016.2638913].

    F. Veirano, L. Alves de Barros Naviner and F. Silveira, Asymmetrical Length Biasing for Energy Efficient Digital Circuits, IEEE Latin American Symposium on Circuits and Systems, Bariloche, Argentina, February 2017.

    A. Stempkovskiy, D. Telpukhov, R. Solovyev, E. Balaka and L. Alves de Barros Naviner, Practical metrics for evaluation of fault-tolerant logic design, IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering , Saint Petersbourgh, Russia, February 2017, pp. 569-573.

    W. Zhao, Y. Wang and L. Alves de Barros Naviner, Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy, Materials Science Journal, January 2017, vol. 9, n° 41, pp. 1-17.

  • 2016

    F. Veirano, F. Silveira and L. Alves de Barros Naviner, Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS, Journal of Low Power Electronics, December 2016, vol. 12, pp. 74-81.

    F. B. Armelin, L. A. d. B. Naviner, R. d'Amore and I. A. Azevedo, Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2016, pp. 277-280 [DOI 10.1109/ICECS.2016.7841186].

    Y. Wang, H. Cai, L. A. B. Naviner, W. Zhao, Y. Zhang, J.-O. Klein, X. Zhao and M. Slimani, A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI, Microelectronics Reliability, September 2016 [hal-01371736, v1] [DOI 10.1016/j.microrel.2016.07.073].

    Y. Wang, H. Cai, L. A. B. Naviner, Y. Zhang, X. Zhao, M. Slimani, J.-O. Klein and W. Zhao, A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI, ESREF 2016 27th EUROPEAN SYMPOSIUM ON RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS, Händel-Halle, Halle (Saale), Germany, September 2016 [hal-01371743, v1] [DOI 10.1016/j.microrel.2016.07.073].

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Breakdown Analysis of Magnetic Flip-flop With 28nm UTBB FDSOI Technology, IEEE Transactions on Device and Materials Reliability, September 2016, vol. 16, n° 3, pp. 376-383.

    H. Cai, K. Liu, L. Alves de Barros Naviner, Y. Wang, M. Slimani and J.-F. Naviner, Efficient reliability evaluation methodologies for combinational circuits, Microelectronics Reliability, September 2016, vol. 64.

    F. Veirano, F. Silveira and L. A. d. B. Naviner, Pushing Minimum Energy Limits by Optimal Asymmetrical Back Plane Biasing in 28 nm UTBB FD-SOI, Proceedings of International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Bremen, Germany, September 2016, pp. 243-249.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost, IEEE Transactions on Magnetics, August 2016, vol. 52, n° 8, pp. 1-7.

    Y. Wang, H. Cai, L. A. B. Naviner, J.-O. Klein, J. Yang and W. Zhao, A novel circuit design of true random number generator using magnetic tunnel junction, 12th ACM/IEEE International Symposium on Nanoscale Architectures, Beijing,China, July 2016 [ hal-01371756, version 1] [DOI 10.1145/2950067.2950108].

    M. Slimani, L. Alves de Barros Naviner, Y. Wang and H. Cai, Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters, Microelectronics Reliability, July 2016, vol. C, n° 64, pp. 48-53.

    Y. Wang, H. Cai, L. A. B. Naviner, J.-O. Klein, J. Yang and W. Zhao, A novel circuit design of true random number generator using magnetic tunnel junction, 12th ACM/IEEE International Symposium on Nanoscale Architectures, Beijing,China, July 2016.

    B. Coeffic, V. Malherbe, J.-M. Daveau, G. Gasiot, L. A. B. Naviner, J.-L. Autran and Ph. Roche, A Layout-Based Fault Injection Methodology for SER Prediction: Implementation and Correlation with 65nm Heavy Ion Experimental Results, Proceedings of IEEE Nuclear and Space Radiation Effects Conference (NSREC), New Orleans, USA, July 2016.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Approximate Computing in MOS/Spintronic Non-Volatile Full-Adder, 12th ACM/IEEE International Symposium on Nanoscale Architectures, Beijing, June 2016.

    N. Jovanovic, O. Thomas, E. Vianello, B. Nikolic and L. A. B. Naviner, Design Considerations for Reliable OxRAM-based Non-Volatile Flip-Flops in 28nm FD-SOI Technology, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1146-1149 [DOI 10.1109/ISCAS.2016.7527448].

    N. Jovanovic, O. Thomas, E. Vianello, B. Nikolic and L. A. B. Naviner, Design Considerations for Reliable OxRAM-based Non-Volatile Flip-Flops in 28,m FD-SOI Technology, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1146-1149 [DOI 10.1109/ISCAS.2016.7527448].

    Y. Wang, H. Cai, L. A. B. Naviner, Y. Zhang, X. Zhao, E. Y. Deng, J.-O. Klein and W. Zhao, Compact Model of Dielectric Breakdown in Spin Transfer Torque Magnetic Tunnel Junction, IEEE Transactions on Electron Devices, April 2016, vol. 63, n° 4, pp. 1762-1767 [hal-01318736] [DOI 10.1109/TED.2016.2533438].

    B. Coeffic, J.-M. Daveau, G. Gasiot, A.E. Pricco, S. Parini, T. Scholastique, L. A. B. Naviner and Ph. Roche, Radiation Hardening Improvement of a SerDes under Heavy Ions up to 60 MeV.cm2/mg by Layout-Aware Fault Injection, Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Austin, Texas, USA, March 2016.

    P. Butzen, M. Slimani, Y. Wang, H. Cai and L. Alves de Barros Naviner, Reliable majority voter based on spin transfer torque magnetic tunnel junction device, IEEE Electronics Letters, January 2016, vol. 52, n° 1, pp. 47-49.

    W. Zhao, X. Zhao, Y. Wang, L. Alves de Barros Naviner and D. Ravelosona, Failure analysis in magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy, Materials Science Journal, January 2016, vol. 9, n° 41, pp. 1-17.

    X. Pons Masbernart, Ch. Gruet, E. Georgeaux and L. A. B. Naviner, Battery share algorithm to reduce the energy during scanning procedures, 2016.

  • 2015

    M. Slimani and L. A. B. Naviner, A Tool for Transient Fault Analysis in Combinational Circuits, IEEE International Conference on Electronics, Circuits, and Systems, Caire, Egypte, December 2015.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28nm FDSOI technology, Microelectronics Reliability, October 2015.

    H. Cai, Y. Wang, W. Zhao and L. Alves de Barros Naviner, Multiplexing Sense Amplifier Based Magnetic Flip Flop in 28nm FDSOI Technology, IEEE Transaction on Nanotechnology, October 2015, vol. 14, n° 4.

    H. Cai, Y. Wang, K. Liu, L. Alves de Barros Naviner, H. Petit and J.-F. Naviner, Cross-layer investigation of continuous-time sigma–delta modulator under aging effects, Microelectronics Reliability, October 2015, n° 3, pp. 645.

    H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao, Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28nm FDSOI technology, 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Toulouse, France, October 2015.

    M. Slimani, A. Ben Dhia and L. Alves de Barros Naviner, A Novel Analytical Method for Defect Tolerance Assessment , European Symposium on Reliability of Electron devices, Failure physics and Analysis , Toulouse, France, October 2015 [hal-01216726].

    M. Slimani, A. Ben Dhia and L. Alves de Barros Naviner, A Novel Analytical Method for Defect Tolerance Assessment , Microelectronics Reliability Journal, October 2015, vol. 55, pp. 1285-1289 [hal-01216729].

    N. Jovanovic, E. Vianello, O. Thomas, B. Nikolic and L. A. B. Naviner, Design insights for reliable energy efficient OxRAM-based flip-flop in 28nm FD-SOI, Proceedings of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Sonoma Valley, CA, USA, October 2015.

    Y. Wang, H. Cai, L. A. B. Naviner, Y. Zhang, J.-O. Klein and W. Zhao, Compact thermal modeling of spin transfer torque magnetic tunnel junction, Microelectronics Reliability, September 2015, vol. 9, n° 55, pp. 1649–1653 [hal-01216419] [DOI 10.1016/j.microrel.2015.06.029].

    Y. Wang, H. Cai, L. A. B. Naviner, Y. Zhang, J.-O. Klein and W. Zhao, Compact thermal modeling of spin transfer torque magnetic tunnel junction, ESREF 2015 26th EUROPEAN SYMPOSIUM ON RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS, Toulouse,France, September 2015 [hal-01216389] [DOI 10.1016/j.microrel.2015.06.029].

    F. Veirano, F. Silveira and L. A. d. B. Naviner, Is intrinsic noise a limiting factor for subthreshold digital logic in nanoscale CMOS?, Proceedings of International Workshop on CMOS Variability (VARI), Salvador, Brazil, September 2015, pp. 45-50.

    X. Pons Masbernart, Ch. Gruet, E. Georgeaux and L. A. d. B. Naviner, An Energy Efficient D2D LTE Structure for MPR Based on FlashLinQ, Proceeding of International Symposium on Wireless Communication Systems (ISWCS), Brussels, Belgium, August 2015.

    X. Pons Masbernart, Ch. Gruet, E. Georgeaux and L. A. B. Naviner, D2D Broadcast Communications for 4G PMR Networks, Proceedings of IFIF International Conference on New Technologies, Mobility and Security (NTMS), Paris, France, July 2015.

    L. Alves de Barros Naviner, H. Cai, Y. Wang, W. Zhao and A. Ben Dhia, Stochastic Computation With Spin Torque Transfer Magnetic Tunnel Junction, IEEE-NEWCAS, Grenoble, France, June 2015.

    C. Bottoni, B. Coeffic, J.-M. Daveau, G. Gasiot, F. Abouzeid, S. Clerc, L. A. d. B. Naviner and Ph. Roche, Frequency and Voltage Effects on SER on a 65nm Sparc-V8 Microprocessor Under Radiation Test, Proceedings of IEEE International Reliability Physics Symposium (IRPS), Monterrey, CA, USA, April 2015.

    A. Ben Dhia, M. Slimani, H. Cai and L. Alves de Barros Naviner, A dual-rail compact defect-tolerant multiplexer, Microelectronics Reliability Journal, March 2015, vol. 55, pp. 662-670 [hal-01128326].

    C. Bottoni, B. Coeffic, J.-M. Daveau, G. Gasiot, L. A. d. B. Naviner and Ph. Roche, A Layout-Aware Approach to Fault Injection for Improving Failure Mode Prediction, Proceedings of Workshop on Silicon Errors in Logic - System Effects (SELSE), Austin, USA, March 2015.

    C. Bottoni, B. Coeffic, J.-M. Daveau, L. A. d. B. Naviner and Ph. Roche, Partial Triplication of a Sparc-V8 Microprocessor Using Fault Injection, Proceedings of IEEE Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, February 2015.

    T. An, K. Liu, H. Cai and L. Alves de Barros Naviner, Accurate Reliability Analysis of Concurrent Checking Circuits Employing An Efficient Analytical Method, Microelectronics Reliability, January 2015, vol. 55, n° 3-4, pp. 696-703 [hal-01122423].

    A. Ben Dhia and L. Alves de Barros Naviner, Designing a Robust Mesh of Clusters FPGA : Hardening Basic Blocks, Lambert Academic Publishers, Saarbrücken, Germany, 2015, pp. 116 [DOI ISBN : 978-3-659-66283-6].

    X. Pons Masbernart, E. Georgeaux, Ch. Gruet, F. Montaigne and L. Alves de Barros Naviner, in Wireless Public Safety Networks: Overview and Challenges, ISTE Press & Elsivier, London, United Kingdom, 2015, chap. From DMO to D2D, pp. 9-126.

  • 2014

    Ch. Gruet, E. Georgeaux, H. Gromat, X. Pons Masbernart et L. Alves de Barros Naviner, Procédé permettant d'établir une stratégie d'économie d'énergie de batterie de terminaux mobiles, Décembre 2014, n° WO Patent App. PCT/EP2013/003,489.

    X. Pons Masbernart, A. Mesodiakaki, Ch. Gruet, L. A. d. B. Naviner, F. Adelantado, L. Alonso and C. Verikoukis, An energy efficient vertical handover decision algorithm, Proceedings of IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD), Austin USA, December 2014, pp. 1145-1150.

    X. Pons Masbernart, S. Althunibat, G. Kibalya, Ch. Gruet, L. A. B. Naviner and F. Granelli, Battery-aware network discovery algorithm for mobile terminals within heterogeneous networks, Proceedings of IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD), Athens, Greece, December 2014.

    Y. Wang, Y. Zhang, E. Y. Deng, J.-O. Klein, L. Alves de Barros Naviner and W. Zhao, Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses, Microelectronics Reliability, October 2014, vol. 54, pp. 1774-1778.

    Y. Wang, Y. Zhang, E. Y. Deng, J.-O. Klein, L. Alves de Barros Naviner and W. Zhao, Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Berlin, Germany, October 2014.

    H. Cai, K. Liu and L. Alves de Barros Naviner, A Study of Statistical Variability-aware Methods, IEEE International Symposium on Radio Frequency Integration Technology (RFIT), Hefei, Chine, August 2014.

    A. Ben Dhia, M. Slimani and L. Alves de Barros Naviner, Comparative Study of Defect-Tolerant Multiplexers for FPGAs, 20th IEEE International On-Line Testing Symposium (IOLTS), Platja d'Aro, Spain, July 2014, pp. 7-12 [hal-01062059].

    S. Sarrazin, S. Evain, I. Miro Panades, A. Valentian, L. Alves de Barros Naviner and V. Gherman, Flip-flop selection for in-situ slack-time monito- ring based on the activation probability of timing-critical paths., IEEE International On-line Test Symposium , July 2014.

    S. Nascimento Pagliarini, L. Alves de Barros Naviner, J.-F. Naviner and D. Pradhan, A hybrid reliability assessment method and its support of sequential logic modelling, IEEE International On-line Test Symposium , Platja d'Aro, Spain, July 2014.

    S. U. Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin-Avot, L. A. B. Naviner, E. Amouri, H. M. Mehrez and Z. Marrakchi, Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, July 2014.

    T. An, K. Liu, H. Cai and L. Alves de Barros Naviner, Efficient Implementation for Accurate Analysis of CED Circuits Against Multiple Faults, 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Lublin, Poland, June 2014.

    A. Ben Dhia, M. Slimani and L. A. B. Naviner, A Defect-Tolerant Multiplexer Using Differential Logic for FPGAs, IEEE 21st Mixed Design of Integrated Circuits and Systems Conference (MIXDES), Lublin, Poland, June 2014, pp. 375-380 [hal-01062063].

    H. Cai, K. Liu and L. Alves de Barros Naviner, Reliability-aware Delay Faults Evaluation of CMOS Flip-Flops, 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Lublin, Poland, June 2014.

    C. Bottoni, J.-M. Daveau, G. Gasiot, L. Alves de Barros Naviner and Ph. Roche, Heavy ions test result on a 65nm sparc-v8 radiation-hard microprocessor, IEEE International Reliability Physics Symposium, Waikoloa, Hawai, USA, June 2014.

    N. Jovanovic, O. Thomas, E. Vianello, J.-M. Portal, B. Nikolic and L. A. B. Naviner, OxRAM-Based Non Volatile Flip-Flop in 28nm FDSOI, Proceedings of IEEE NEWCAS Conference (NEWCAS), Trois Rivieres, Canada, June 2014.

    T. An, H. Cai and L. Alves de Barros Naviner, Simulation Study of Aging in CMOS Binary Adders, MIPRO 37th International Convention/Microelectronics, Electronics and Electronic Technology, Opatija, Croatia, May 2014.

    T. An, K. Liu and L. Alves de Barros Naviner, Analytical method for reliability assessment of concurrent checking circuits under multiple faults, MIPRO 37th International Convention/Microelectronics, Electronics and Electronic Technology, Opatija, Croatia, May 2014.

    M. Slimani, A. Ben Dhia and L. A. B. Naviner, Cross Logic : A New Approach for Defect-Tolerant Circuits, IEEE International Conference on IC Design and Technology (ICICDT), Austin, USA, May 2014, pp. 1-4 [hal-01062064].

    L. Alves de Barros Naviner, K. Liu, H. Cai and J.-F. Naviner, Efficient Computation of Combinational Circuits Reliability Based on Probabilistic Transfer Matrix, International Conference on IC Design and Technology (ICICDT), Austin, USA, May 2014.

    S. Sarrazin, S. Evain, I. Miro Panades, A. Valentian, S. Pajaniradja, L. Alves de Barros Naviner and V. Gherman, Shadow-scan design with low latency overhead and in-situ slack-time monitoring, IEEE European Test Symposium, Paderborn, Germany, May 2014.

    A. Ben Dhia, M. Slimani and L. Alves de Barros Naviner, Improving the Robustness of a Switch Box in a Mesh of Clusters FPGA, 15th IEEE Latin American Test Workshop (LATW), Fortaleza, Brazil, March 2014, pp. 1-6 [hal-01062066].

    P. Maris Ferreira, H. Cai and L. Alves de Barros Naviner, in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, IGI Global, Hershey, Pennsylvania (USA), 2014, chap. Reliability Aware AMS/RF Performance Optimization.

    Ch. Gruet, E. Georgeaux, H. Gromat, X. Pons Masbernat et L. A. B. Naviner, Procede permettant d'etablir une strategie d'economie d'energie de batterie de terminaux mobiles, 2014.