# Synchronous Logic

1. Exercise 1 . (Flip Flop)
2. A flip-flop D samples its input at each rising edge of the clock signal. Suppose we want to
3. replace such systematic sampling by a controlled sampling so that new input data is sampled
4. only when a control signal CMD is 010. Derivate a structure allowing this controlled sampling.
5. Figure 1 – Timing diagram of a flip-flop D with controlled sampling.
6. Exercise 2 . (Basics on Architecture)
7. We are interested in defining the architecture of a processor PROC. The input signal of PROC,
8. x, is sampled at the clock frequency fs. The output signals of PROC are given by the equations
9. (1), (2), and (3). Notice that n denotes the signal’s age. For example, xn denotes the n-th sample
10. of x. The processor PROC is supposed to be implemented using registers R in addition to
11. combinational operators OP1 and OP2 (that perform operations OP1 and OP2, respectively).
12. The operator OP2 is commutative.
13. yn = OP2(xn;wn􀀀2) (1)
14. wn = OP2[OP1(wn􀀀2);OP1(zn􀀀2)] (2)
15. zn = OP2[(OP1(yn);OP1(wn)] (3)
16. (1) Derivate a parallel architecture for the processor PROC. Notice that ”parallel” architecture
17. means that at each graph’s node corresponds a separate operator.
18. (2) Suppose propagation delays tOP1 = tOP2 = 25ns. Suppose ideal register delay (tR = 0).
19. Derivate the maximal frequency (fmax1) of the proposed PROC.
20. (3) If fmax1 < 20 MHz, make changes in your architecture in order to obtain fmax2 20 MHz.
21. (4) Try to make changes in order to obtain fmax3 40 MHz. What are your conclusions ?
22. (5) Derivate a sequential architecture for the processor PROC. Notice that ”sequential” architecture
23. means that it’s based on only one OP1 and only one OP2. Let 1n
24. and 2n
25. be the
26. outputs of OP1 and OP2, respectively. All registers R are supposed to be ideal (tR = 0).
27. The proposed architecture should allow processing of input samples x at a rate 10MHz.
28. What is the minimal clock frequency ? Sketch a timing diagram showing y, w, z, 1 and
29. 2 evolution for two consecutive calculations, i.e. n and n + 1.
30. Page 1
31. Telecom ParisTech Synchronous Logic Prof. Lirida Naviner
32. Exercise 3 . (Basics on Architecture)
33. Let be the iterative algorithm presented in the graph of the figure bellow. An iteration consists
34. on one step of calculation (represented by cercles) followed by one step of wire multiplexing.
35. The calculation step needs 8 operations OP on a set of 16 operands (D0 to D15). Consider
36. the sampling period of operands (D0 to D15) is 51:2s. Consider an application requiring 256
37. iterations of a such algorithm. Also consider you dispose of registers and fully combinational
38. operators OP that perform the operation OP shown in the nodes of the given graph. The
39. operators have propagation delay tOP = 250ns. The registers have total delay tR = 2:5ns.
40. OP
41. OP
42. OP
43. OP
44. OP
45. OP
46. OP
47. OP
48. OP
49. OP
50. OP
51. OP
52. OP
53. OP
54. OP
55. OP
56. D01
57. D03
58. D04
59. D06
60. D09
61. D011
62. D012
63. D014
64. D00
65. D02
66. D05
67. D07
68. D08
69. D010
70. D013
71. D015
72. D0
73. D1
74. D2
75. D3
76. D4
77. D5
78. D6
79. D7
80. D8
81. D9
82. D10
83. D11
84. D12
85. D13
86. D14
87. D15
88. Figure 2 – Calculation graph.
89. (1) Give the maximal operation frequency fmax accepted by operator OP.
90. (2) Give the computation power required by the application (in OP/s).
91. (3) Let be the implementation of the algorithm based on only one pipelined operator OP. How
92. many pipeline barriers are required ?
93. (4) Consider the pipelined operator OP of previous item. Give the sequence of operations for
94. two consecutive iterations. What are your conclusions ?

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